What is the US QuickTurn PCB manufacturing policy?
1. Orders are not guaranteed to be accepted by us until your files pass our Smart DFM review.
2. We prefer that you pass your design through Smart DFM. This way, you can correct any errors that you find. At the end of the Smart DFM process, you can save a .ezq file. If there are no errors, then we can manufacture your quickturn prototype printed circuit boards directly from the .ezq file. If you get stuck in the middle of the Smart DFM process, you can save and submit your .ezq file to us for additional help.
3. While we prefer that you send us a file after passing it through Smart DFM, you can also choose to send us your raw Gerber and Drill files. We will process your files using Smart DFM and send you an email with a detailed result of the Smart DFM checks. If possible, we will edit your files to remove any Smart DFM violations. Our email to you will detail any changes that we've made and we will send a revised .ezq file that you can load into any of our ViewMate family of products. You can review all of the suggested changes that we've made. If you're happy with our changes, then you can ask us to produce your PCB using the supplied .ezq file. However, we recommend that you change your design in your CAD system so that it passes our Smart DFM checks without requiring any alterations.
4. All files will be retained for 3 months.
5. Orders can be shipped anywhere in the world that is served by UPS or FedEx, so long as no US Export restrictions are in force.
6. We reserve the right to change prices and delivery terms at any time.
If your design contains non-plated holes
Smart DFM places plated and non-plated holes on separate layers. If you run your design through Smart DFM, please remember to check the "Non-Plated Through Holes" check box.
If you send us raw Gerber and Drill files, and your design contains both plated and non-plated holes, then we prefer that you place these holes on separate layers. This will ensure that we understand your intent. If you are using ViewMate Deluxe or ViewMate Pro, then you can also submit your data as a .bin file. Name your plated drill layer "PlatedDrills" and your non-plated drill layer "NonPlatedDrills".
QuickTurn Printed Circuit Board Outlines
Your prototype printed circuit board outline does not have to be square or rectangular. You can submit round boards or boards with a complex shape. Our requirement is that we can convert your outline to a continuous unbroken path. By default, we will rout your board outline with a 0.0625" diameter rout bit. This will result in a minimum radius of approximately 0.032" on inside corners. If your design contains inside corners with radii of less than 0.032", then we will use a 0.03125" diameter rout tool to cut out your board. In this case, inside corners will have a minimum radius of 0.016".
Routing
Default rout tool diameter is 0.0625".
All features are cut out using this tool if possible (both internal features and the board outline).
Internal Cutouts
Your design can have both plated and non-plated internal cutouts. We suggest that you add one layer for each type of cutout (plated or non-plated). Just place elements in these layers that are the exact shape of the cutout that you want. For example, if you want a 0.050" x 1.00" slot cutout of the board, then just add a trace of this size to the appropriate layer. If you have a more complex shape, then just submit it as one or more polygons that describe the edge of the cutout. We suggest you draw the polygon with an "F-Type" shape (a line of zero width). If you choose, you can draw the polygons with any width trace. We assume that the centerline of the trace describes the edge of your internal cutout. Plated cutouts will have the inside of the cutout plated with the finish that you choose (Tin/Lead or OSP RoHS). Non-plated cutouts will not have any plating on the internal edges. Name your plated cutouts layer "PlatedInternalRouts". Name your non-plated internal routs "NonPlatedInternalRouts". If you wish, you can also supply a drawing that details the internal cutouts and we will create the needed geometry for you. We prefer to use a 0.0625" rout bit for internal cutouts, although we will use a 0.03125" diameter bit if your design contains features with internal radii of less than 0.032".
Solder Mask Swell and "Minimum Web"
When manufacturing your prototype circuit board, there may be a small misregistration between the solder mask layers and the underlying copper layers. As a result, we recommend that you swell your solder mask layer so that it is 0.005" (0.0025" on a side) larger than the underlying copper elements. This way, if there is a misregistration, then your copper pads will not have any solder mask on them. You should also ensure that your design has a "Minimum Web" of at least 0.003" between adjacent pads. Smart DFM can pinpoint any problem areas for you.
Silk Screen Feature Size
We recommend that your silk screen features have a width of at least 0.007", although the absolute minimum for clear legibility is 0.005". If you submit a Smart DFM file with features that are less than 0.005", then we will simply submit your design for manufacture. There is no guarantee that these narrow features will reproduce correctly. If you submit Gerber data or a .bin file to us, then we will modify your silk screen layers if any features are less than 0.007". If possible, we will set all features so that the minimum trace width is 0.007". Where this is impractical, we will reduce the silk screen feature size to a minimum of 0.005".
Do Printed Circuit Boards UL marking?
By default we add a UL marking to the bottom copper layer:
If the large UL logo will not fit on your prototype circuit board, then we will add the smaller logo shown below:
We add a Date Code, a 3 digit order fragment and a Serial Number to the bottom silk screen layer:
2-LAYER PCB
L1 1oz Cu ----------
.059" DIELECTRIC
L2 1oz Cu ----------
4-LAYER PCB
L1 1oz Cu ----------
.0085" DIELECTRIC
L2 .5oz Cu ----------
.039" DIELECTRIC
L3 .5oz Cu ----------
.0085" DIELECTRIC
L4 1oz Cu ----------
6-LAYER PCB
L1 1oz Cu ----------
.0048" DIELECTRIC
L2 .5oz Cu ----------
.020" DIELECTRIC
L3 .5oz Cu ----------
.0048" DIELECTRIC
L4 .5oz Cu ----------
.020" DIELECTRIC
L5 .5oz Cu ----------
.0048" DIELECTRIC
L6 1oz Cu ----------
8-LAYER PCB
L1 1oz Cu ----------
.005" DIELECTRIC
L2 .5oz Cu ----------
.010" DIELECTRIC
L3 .5oz Cu ----------
.005" DIELECTRIC
L4 .5oz Cu ----------
.010" DIELECTRIC
L5 .5oz Cu ----------
.005" DIELECTRIC
L6 .5oz Cu ----------
.010" DIELECTRIC
L7 .5oz Cu ----------
.005" DIELECTRIC
L8 1oz Cu ----------
10-LAYER PCB
L1 1oz Cu ----------
.005" DIELECTRIC
L2 .5oz Cu ----------
.010" DIELECTRIC
L3 .5oz Cu ----------
.005" DIELECTRIC
L4 .5oz Cu ----------
.010" DIELECTRIC
L5 .5oz Cu ----------
.005" DIELECTRIC
L6 .5oz Cu ----------
.010" DIELECTRIC
L7 .5oz Cu ----------
.005" DIELECTRIC
L8 .5oz Cu ----------
.010" DIELECTRIC
L9 .5oz Cu ----------
.005" DIELECTRIC
L10 1oz Cu ----------
What is the minimum trace width allowed?
The minimum traces width is 0.005" (5 mils).
What is the minimum spacing between traces to copper lands?
The minimum gap between traces and copper lands is 0.005" (5 mils).
What is the minimum annular ring on vias?
The minimum annular ring on vias is 0.005" (5 mils). each side of the hole. The pad must be large enough to tent over the hole otherwise you may lose the metal in the hole during outer layer etching resulting in plating voids.
What is the closest copper to edge of the printed circuit board?
The closest copper trace and land fills to edge of PC board is 0.010" (10 mils). If the copper runs closer to the edge it may be exposed during board rout.
Are the prototype printed circuit boards electrically tested?
All multi-layer (4, 6, 8 and 10 layer) PCB prototypes come electrically tested as part of the service. Two-layer boards are not tested.
Can you handle controlled impedance requirements?
No. This feature is not available through the US Quickturn PCBs service. However, you may submit a Custom_RFQ for complete prototype circuit board manufacturing needs.
To what acceptability standards do you build?
PCBs are built to IPC-A-6011/6012 latest revision Class 2 with inspection based on IPC-A-600 latest revision.
What is OSP finish?
OSP (Organic Solderability Preservative) is a thin organic coating deposited on the exposed copper. The coating preserves the solderability of the copper surface, while allowing it to be easily soldered without the need for removal. Excellent solderability is maintained through 3 to 5 I.R. soldering cycles.
What files do you need to manufacture my US Quickturn PCBs?
The following files need to be compressed into one ZIP file and uploaded through the US Quickturn PCBs web site at order placement. Our web application will only accept one ZIP file per order. Your file set needs to be complete with the following data:
1. Gerber files in 274X or 274D formats. (274D format will require an aperture list or environment file)
2. Excellon2 NC drill file.
3. Drill tool list specifying finished hole sizes, hole quantities, and plated/non-plated holes.
How do I send my files?
You will be prompted to upload your files through the web site during order placement. Your files are encrypted and maintained in our secure database.
If you have more questions, please contact our Technical Experts at support@pcbunlimited.com
